library ieee;
use ieee.std_logic_1164.all;
library altera;
use altera.altera_syn_attributes.all;

entity mii_phy is
	port (
		SWITCHES : in std_logic_vector(15 downto 0);
		LED_RED : out std_logic_vector(17 downto 0);
		LED_GREEN : out std_logic_vector(8 downto 0);
		IO : inout std_logic_vector(35 downto 0);
		EXT_CLK : in std_logic;
		--GPIO_1 : in std_logic_vector(0 to 35);
		RX_DATA : out std_logic_vector(3 downto 0);
		RX_CLK : inout std_logic;
		RX_DV : out std_logic;
		TX_DATA : out std_logic_vector(3 downto 0);
		TX_CLK : inout std_logic;
		TX_DV : out std_logic
	);
end mii_phy;

architecture structure of mii_phy is

begin		
	RX_DATA <= IO(3 downto 0);
	IO(34) <= RX_CLK;
	RX_CLK <= EXT_CLK;
	RX_DV <= IO(4);
	TX_DATA <= IO(9 downto 6);
	IO(35) <= TX_CLK;
	TX_CLK <= EXT_CLK;
	TX_DV <= IO(5);
	
	--for reference...
	--rcv_clk => GPIO_0(5),
	--xmt_clk => GPIO_0(12),
	--in_port_to_the_rcv_data => GPIO_0(0 TO 3),
	--in_port_to_the_rcv_dv => GPIO_0(4),
	--out_port_to_the_xmt_data => GPIO_0(6 TO 9),
	--out_port_to_the_xmt_dv => GPIO_0(10)
	
	
	--TX_DV <= '1';
	LED_GREEN(8 downto 0) <= "101010101";
end structure;